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Modellering av lateral PNP-transistor i CMOS-process
2001 (Swedish)Independent thesis Basic level (professional degree)Student thesis
Abstract [sv]

Denna rapport beskriver arbetet med att analysera en speciell transistor-struktur som finns i CMOS-processer, sk laterala PNP-transistorer. Dessa är alltså bipolära transistorer som ofta betraktas som rena parasit-element men har faktiskt några positiva egenskaper såsom lågt brus, hög branthet mm. Problemet är att dessa PNP-transistorer är mycket dåligt modellerade i alla simulatorer. Arbetet har bestått i att mäta upp prestanda för laterala PNP-transistorer i två olika CMOS-processer, 2,0 mm och 0,5 mm. Med hjälp av denna data bestämdes DC-parametrar och utifrån dessa skapades en SPICE-kompatibel sk subcircuit modell. Modellen stämmer bra vid kollektorströmmar över 1 mA. När det gäller 2,0 mm-processen blev resultatet sämre.

Abstract [en]

This report describes the work of analysing a special kind of transistor-structure that is present in CMOS-processes, so called lateral PNP-transistors. These are bipolar transistors, which often are considered to be purely parasitic devices, but they do have some positive characteristics such as low noise and high forward transconductance. The problem is that these PNP-transistors are very poorly modelled in all simulators. The work has consisted of measuring the performance of lateral PNP-transistors in two different CMOS-processes, 2,0 mm and 0,5 mm. From the measured data DC-parameters were extracted, and out of these parameters a SPICE compatible subcircuit model was created. The model has a good fit at collector currents above 1 mA. The result for the 2,0 mm-process was a bit worse.

Place, publisher, year, edition, pages
2001. , 25 p.
Identifiers
URN: urn:nbn:se:kau:diva-54255Local ID: ELI-4OAI: oai:DiVA.org:kau-54255DiVA: diva2:1102957
Subject / course
Electronic Engineering, Bachelor of Science
Available from: 2017-05-30 Created: 2017-05-30

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  • apa
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  • de-DE
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  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
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